Clock gating is a technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating saves power by adding more logic to a circuit to prune a clock tree. Pruning the clock disables portions of the circuitry so that the flip-flops and logic in the circuitry do not switch states. Switching states consumes power. When digital circuitry is not being switched, the switching power consumption goes to approximately zero, where only small leakage currents are incurred.
Clock gating works by controlling the enable conditions attached to registers, and uses that control to gate the clocks. The clock gating may reduce the die area, as well as reduce power consumption. However, the clock gating logic can also change the clock tree structure, since the clock gating logic may be part of the clock tree.